Category: Hardware verification languages

OpenVera
OpenVera was a hardware verification language developed by System Science and acquired by Synopsys.
Reference Verification Methodology
The Reference Verification Methodology (RVM) is a complete set of metrics and methods for performing Functional verification of complex designs such as for Application-specific integrated circuits or
E Reuse Methodology
The e Reuse Methodology (eRM) was the first reuse methodology to emerge in the Hardware Verification Language space and was used in conjunction with the e Hardware Verification Language. It was invent
SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on
SystemVerilog DPI
SystemVerilog DPI (Direct Programming Interface) is an interface which can be used to interface SystemVerilog with foreign languages. These foreign languages can be C, C++, SystemC as well as others.
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes,
Property Specification Language
Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extens
Hardware verification language
A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a h
E (verification language)
e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification testbenches.
Specman
Specman is an EDA tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments writte
SystemC AMS
SystemC AMS is an extension to SystemC for analog, mixed-signal and RF functionality. The SystemC AMS 2.0 standard was released on April 6, 2016 as IEEE Std 1666.1-2016.